1. Field of the Invention
The present invention relates to a current mirror circuit and an analog-digital converter. More particularly, the present invention relates to a current mirror circuit and an analog-digital converter, in which a current mirror having a high accuracy can be obtained even at a low power supply voltage.
2. Description of the Related Art
A current mirror circuit is a circuit for sending to a second transistor connected to a first transistor the same current as the current flowing through the first transistor or the proportional current, as if it is a mirror.
Typically, a drain current IDS of a MOS transistor in a saturation region is given by:
IDS=(xc2xd)xc3x97xcexcxc3x97COXxc3x97(W/L)xc3x97(VGSxe2x88x92Vt)2xc3x97(1+xcexxc3x97VDS)xe2x80x83xe2x80x83(1)
In the equation (1), xcexc is a mobility of a carrier, COX is a thickness of gate oxide film, L is a length of a channel, W is a width of the channel, Vt is a threshold voltage, VGS is a voltage between a gate and a source, VDS is a voltage between a drain and the source, and xcex is a channel length modulation coefficient.
In the usual current mirror circuit, as indicated by the equation (1), even if the gate-source voltages VGS are equal to each other, a drain-to-source voltage VDS of an NMOS transistor on an input side is different from that of an NMOS transistor on an output side. For this reason, the channel length modulation effect resulting from the channel length modulation coefficient xcex causes a large error to occur between an input current (standard current Iin) and an output current Iout. In order to reduce this error resulting from the channel length modulation effect, the counter-plan is typically carried out by designing the current mirror circuit as a cascode connection and the like.
The cascode current mirror circuit is disclosed in, for example, xe2x80x9cAnalog Integrated Circuit Design Technique, Low Part (1990) p286-288xe2x80x9d written by Gray et al. An output resistance of the current mirror circuit can be increased by designing the current mirror circuit as the cascode connection. As a result, it is possible to reduce the error caused by the channel length modulation effect.
As a conventional example of a related current mirror circuit, Japanese Laid Open Patent Application (JP-A 2000-114891) discloses xe2x80x9cCurrent Source Circuitxe2x80x9d.
FIG. 1 is a circuit diagram showing the configuration of that current mirror circuit.
A current mirror circuit 101 is provided with an operational amplifier 111, a constant current source 130, and N-channel MOS transistors Q101, Q102 and Q103. Hereafter, the N-channel MOS transistor is referred to as an NMOS transistor.
A high potential side voltage source (not shown) is connected to one of both terminals of a constant current source 130, and a power supply voltage VDD is inputted/supplied. A drain of the NMOS transistor Q101 and a non-inverting input terminal of the operational amplifier 111 are connected to the other terminal of the constant current source 130. The constant current source 130 outputs the standard current Iin from the other terminal, based on the power supply voltage VDD. The drain of the NMOS transistor Q101 is connected to a gate of the NMOS transistor Q101.
A drain of the NMOS transistor Q102 is connected to an inverting input terminal of the operational amplifier 111 and a source of the NMOS transistor Q103. A gate of the NMOS transistor Q102 is connected to the gate of the NMOS transistor Q101. The sources of the NMOS transistor Q101 and the NMOS transistor Q102 are grounded.
The gate of the NMOS transistor Q103 is connected to an output terminal of the operational amplifier 111. The drain of the NMOS transistor Q103 is connected to an output terminal Z. The output terminal Z is connected to a load circuit (not shown) An output current Iout (the voltage between the terminal Z and the ground: the output voltage Vout) corresponding to the standard current Iin is supplied through the output terminal Z to the load circuit (not shown).
Due to the operational amplifier 111, the drain voltage of the NMOS transistor Q102 is set to be substantially equal to the drain voltage of the NMOS transistor Q101. If the drain voltage of the NMOS transistor Q103 is changed by the variation in the load circuit and the like, the source voltage of the NMOS transistor Q103, namely, the drain voltage of the NMOS transistor Q102 is changed correspondingly to the change. The output voltage of the operational amplifier 111 is also changed on the basis of the change in the drain voltage of the NMOS transistor Q102.
For example, if the drain voltage of the NMOS transistor Q102 is increased and it becomes higher than the drain voltage of the NMOS transistor Q101, a voltage difference between the drain voltages of the NMOS transistors Q101, Q102 is generated correspondingly to the increase in the drain voltage of the NMOS transistor Q102. The output voltage of the operational amplifier 111 is dropped correspondingly to the voltage difference. Since the threshold voltage of the NMOS transistor Q103 is constant, the drop in the gate voltage causes the drop in the source voltage, and the drain voltage of the NMOS transistor Q102 is kept substantially constant. On the other hand, if the drain voltage of the NMOS transistor Q102 is dropped, and it becomes lower than the drain voltage of the NMOS transistor Q101, the output voltage of the operational amplifier 111 is increased correspondingly to the drop in the drain voltage of the NMOS transistor Q102. The source voltage of the NMOS transistor Q103 is increased correspondingly to the increase. Accordingly, this increase suppresses the drop tendency of the drain voltage of the NMOS transistor Q102.
As mentioned above, the variation in the drain voltage of the NMOS transistor Q102 caused by the variation in the load circuit (not shown) connected to the drain of the NMOS transistor Q103 and the like is suppressed by the operational amplifier 111. Accordingly, the drain voltage of the NMOS transistor Q102 is kept at the substantially constant level, namely, at the level equal to the drain voltage of the NMOS transistor Q101. If the NMOS transistors Q101, Q102 are under the same condition, for example, if they have the same size and the same carrier mobility, the same current as the NMOS transistor Q101 flows through the NMOS transistor Q102. That is, the output current Iout substantially equal to the standard current Iin flows through the drain of the NMOS transistor Q103. The output voltage Vout (the voltage between the terminal Z and the ground) corresponding to the output current Iout is supplied to the load circuit (not shown).
The current mirror circuit 101 shown in FIG. 1 can attain the current mirror circuit having the high accuracy since the operational amplifier 111 forcedly makes the drain-to-source voltages of the NMOS transistors Q101, Q102 equal to each other.
According to the above-mentioned technique disclosed in Japanese Laid Open Patent Application (JP-A 2000-114891), it is necessary to operate all the transistors (the NMOS transistors Q101, Q102 and Q103) in the saturation region, in order to normally operate the current mirror circuit 101. That is, it is necessary to operate the NMOS transistors Q101, Q102 and Q103 under the following condition:
VDS greater than VGSxe2x88x92Vtxe2x80x83xe2x80x83(2)
The output side in the current mirror circuit 101 is configured as the longitudinal pile (cascode connection) of the two MOS transistors by the NMOS transistors Q102, Q103. For this reason, for example, when the GND (ground) is used as a standard and the sizes of the transistors (W/L, L: Channel Length, W: Channel Width) are equal to each other, if the substrate effect (back gate effect) is ignored, they are not normally operated unless the value of the output voltage Vout (the voltage between the terminal Z and the ground) is equal to or greater than two times the value (VGSxe2x88x92Vt). That is, the current mirror circuit 101 has the defect that a high accuracy can not be obtained at a low power supply voltage (if the power supply voltage VDD is low). This is because the output side of the current mirror circuit 101 is configured as the longitudinal pile (cascode connection) of the two transistors by the NMOS transistors Q102, Q103.
As the related technique, Japanese Laid Open Patent Application (JP-A 2000-341126) discloses xe2x80x9cD/A Converter And Pressure Sensor Circuit Using The Samexe2x80x9d. This D/A converter is composed of a current mirror circuit, and it includes a constant current circuit and a current-to-voltage converter. In the constant current circuit, an R-2R ladder circuit for determining an output current is connected to a transistor on an output side, and it outputs a current corresponding to a digital value inputted to the R-2R ladder circuit. The current-to-voltage converter outputs a voltage value proportional to an output current of the constant current circuit. Then, this is characterized in that the output voltage of the current-to-voltage converter is outputted.
Therefore, an object of the present invention is to provide a current mirror circuit and an analog-digital converter, in which a current mirror having a high accuracy can be obtained even at a low power supply voltage.
Another object of the present invention is to provide a current mirror circuit and an analog-digital converter, in which a current mirror having a high accuracy can be obtained without any channel length modulation effect.
In order to achieve an aspect of the present invention, the present invention provides a current mirror circuit including: a first constant current source which outputs a constant current to a first node based on a first reference voltage; a first MOS transistor which has a source grounded, a gate connected to a second MOS transistor and a drain connected to the first node; the second MOS transistor which has a source grounded, a gate connected to the first MOS transistor and a drain connected to a second node; a first operational amplifier which has a first input terminal connected to the first node, a second input terminal connected to a third node which is connected to a second reference voltage and an output terminal connected to the gates of the first and second MOS transistors; and a second operational amplifier which has a first input terminal connected to the third node, a second input terminal connected to the second node and an output terminal connected through a feedback circuit to the second node.
In the current mirror circuit, the first constant current source includes: the first reference voltage; a third MOS transistor which has a source grounded, a gate connected to an output terminal of a third operational amplifier and a drain connected to a current mirror circuit with cascode connection; the third operational amplifier which has a first input terminal connected to the first reference voltage, a second input terminal connected to the gate of the third MOS transistor and an output terminal connected to the gate of the third MOS transistor; and the current mirror circuit with cascode connection which is connected to the drain of the third MOS transistor, a power supply voltage and the first node.
The current mirror circuit further includes: a second resistor and a fourth MOS transistor which are connected in series between a power supply voltage and the drain of the second MOS transistor; and
a fifth MOS transistor which is connected in series between the second node and the drain of the second MOS transistor, wherein the second node is connected to a signal voltage through a first resistor.
In order to achieve another aspect of the present invention, the present invention provides an analog-digital converter including: a first constant current source which outputs a constant current to a first node based on a first reference voltage; a first MOS transistor which has a source grounded, a gate connected to a second MOS transistor and a drain connected to the first node; the second MOS transistor which has a source grounded, a gate connected to the first MOS transistor and a drain connected to a second node; a second resistor and a fourth MOS transistor which are connected in series between a power supply voltage and the drain of the second MOS transistor; a fifth MOS transistor which is connected in series between the second node and the drain of the second MOS transistor, wherein the second node is connected to a signal voltage through a first resistor; a first operational amplifier which has a first input terminal connected to the first node, a second input terminal connected to a third node which is connected to a second reference voltage and an output terminal connected to the gates of the first and second MOS transistors; a second operational amplifier which has a first input terminal connected to the third node, a second input terminal connected to the second node and an output terminal connected through a first capacitance to the second node, functioning as an integrator; and
a comparator comparing an output of the second operational amplifier with a predetermined voltage, and outputting the comparison result output.
In the analog-digital converter, the first constant current source includes: the first reference voltage, a third MOS transistor which has a source grounded, a gate connected to an output terminal of a third operational amplifier and a drain connected to a current mirror circuit with cascode connection; the third operational amplifier which has a first input terminal connected to the first reference voltage, a second input terminal connected to the gate of the third MOS transistor and an output terminal connected to the gate of the third MOS transistor; and the current mirror circuit with cascode connection which is connected to the drain of the third MOS transistor, a power supply voltage and the first node.
The analog-digital converter further includes a switching controller controlling a switching operations of the fourth and fifth MOS transistors based on the comparison result output.
The analog-digital converter further includes a sixth and a seventh MOS transistors which are connected in series; and a third reference voltage which is connected to a gate of the sixth MOS transistor, wherein a drain of the sixth MOS transistor is connected to the third node, the first input terminal of the first operational amplifier is connected to a node between the sixth and the seventh MOS transistors, instead of the third node, and a gate of the seventh MOS transistor is connected to the gates of the first and the second MOS transistors.
In the analog-digital converter according to claim 4, wherein the first operational amplifier includes: an eighth and a ninth MOS transistors whose sources are connected to each other; a second constant current source which is connected to the sources of the eighth and ninth MOS transistors; and a tenth and an eleventh MOS transistors whose sources are grounded and their gates are connected to each other, wherein a drain of the tenth MOS transistor is connected to a drain of the eighth MOS transistor and the gate of the tenth MOS transistor, a drain of the eleventh MOS transistor is connected to the gates of the first and the second MOS transistors and the drain of the ninth MOS transistor, the gates of the eighth and the ninth MOS transistors correspond to the first and the second input terminal of the first operational amplifier, the gate of the eighth MOS transistor is connected to the first node, the gate of the ninth MOS transistor is connected to the third node, and the drain of the eleventh MOS transistor corresponds to the output terminal of the first operational amplifier.
The analog-digital converter further includes a compensation circuit which is connected between the gate and the drain of the first MOS transistor.
In the analog-digital converter, the compensation circuit includes a second capacitor and a third resistor which are connected in series, wherein the third resistor is connected to the drain of the first MOS transistor, and the second capacitor is connected to the gate of the first MOS transistor.
In the analog-digital converter, the predetermined voltage is equal to the second reference voltage.